For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue.
Integrated circuits commonly include electrically conductive microelectronic structures, which are known in the arts as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. The interconnects and vias are typically separated from each other by an interlayer dielectric material. As the pitch between interconnect lines and the spacing between layers continues to be scaled down, capacitive coupling between lines and vias increase. Accordingly, typical back-end interconnect stacks utilize low-k dielectric materials to reduce the capacitance. In some back-end interconnect stacks, air-gaps may be used to replace portions of the low k-dielectric materials in order to further decrease the capacitance.
Air-gaps are typically formed with an “air-gap etch” that removes portions of the interlayer dielectric material. After the interlayer dielectric material is removed, a non-conformal material is deposited over the openings formed by the air-gap etch in order to form an intentional “key-hole void”. However, the formation of air-gaps with an air-gap etching process has several disadvantages. For example, unlanded or partially landed vias produce the risk of a short-circuit. During the via formation, an unlanded or partially landed via may punch through the non-conformal fill material and provide an opening into the air-gap. When the via metal is deposited the metal will also fill the air-gap and may result in a short. Accordingly, the risk of shorting the device needs to be mitigated by using additional masks that block the formation of air-gaps near vias. Additionally, the air-gap etching process that is presently used is a dry etching process. Accordingly, the interlayer dielectric material is only able to be removed from between interconnect lines due to the anisotropic nature of dry-etching processes. As such, the dielectric material below the interconnect lines remains behind and there is not a beneficial reduction in the layer-to-layer capacitance.
Thus, improvements are needed in the area of via manufacturing technologies.